The present invention relates generally to circuits for generating event timing signals, and more particularly to phase locked loop circuits.
Phase locked-loop (PLL) circuits are used in numerous applications to generate clock signals, strobe signals and other timing signals. For example, FIG. 1 illustrates a prior-art transceiver device 51 that includes a phase-locked loop (PLL) circuit 53, transmit circuit 55 and receive circuit 57. The PLL circuit 53 generates a transmit clock signal, TCLK, for timing the transmission of data within the transmit circuit 55 and for recovering clock and data (i.e., clock data recovery (CDR)) within the receive circuit 57. Due to closed-loop operation of the PLL circuit 53, the transmit clock signal has a frequency and phase that tracks the frequency and phase of a reference clock signal, CLKREF, and is said to be phase-locked to the reference clock signal.
Because the PLL circuit 53 (like most PLL circuits) is able to achieve phase lock only over a limited range of reference clock frequencies, a reset signal, RST, is asserted at system power up to disable the closed-loop operation of the PLL circuit 53 until after the reference clock signal has reached a steady-state oscillation frequency. FIG. 2 illustrates a typical PLL reset sequence. At time T1, power is applied, ramping the system supply voltage, VS, and enabling oscillation of the reference clock signal (e.g., by powering a crystal oscillator or other clock generator). In the example of FIG. 2, the reference clock frequency is slow at first, then gradually increases to a stabilized, steady-state oscillating frequency. A circuit for generating the reset signal (i.e., the reset signal generator) is typically tuned to the time required for the reference clock frequency to stabilize and is designed to deassert the reset signal (e.g., to a high logic state) for a corresponding reset delay interval, I1, to disable the phase locking operation of the PLL. After the reset delay interval has elapsed, the reset signal generator drives the reset signal low to reset (i.e., enable) the phase locking operation of the PLL circuit 53.
Typically, the reset signal generator is implemented in an integrated circuit (IC or chip), or discrete-component circuit that is distinct from the IC containing the PLL circuit 53. One reason for this is that the reset delay interval is determined by the stabilization time of the reference clock generator (often implemented by a crystal oscillator or other off-chip timing circuit) and therefore tends to vary from system to system according to the choice of reference clock generator. Unfortunately, off-chip generation of the reset signal means that an additional IC pin (or other interface structure) and signal path must be provided to couple the reset signal generator to the PLL circuit 53. Aside from the added fabrication expense and design cost, in some instances it may be impractical to provide an extra pin or signal path for PLL reset purposes; particularly where the IC containing the PLL circuit 53 is required to fit into a previously designed socket, pad array, etc. (i.e., a so-called socket-stealing application) that does not provide for a PLL reset signal. Accordingly, it would be desirable to provide a PLL circuit having a self-resetting capability.
A phase-locked loop (PLL) circuit having a self-resetting function is described in various embodiments. In a first embodiment, a lock control circuit is provided within the PLL circuit to detect when a supply voltage has reached a predetermined level and, in response, to reset the PLL circuit by pulsing a lock enable signal for a predetermined time. In another embodiment, a lock control circuit pulses the lock enable signal for a predetermined time upon detecting that a reference clock signal has reached a threshold oscillation frequency. In either embodiment, the predetermined time may be determined by hardwired circuit components or may be programmable by a host device.
These and other features and advantages of the present invention are described in the detailed description below.